RISC-V is a new instruction set architecture originally designed to support computer architecture research and education at UC Berkeley. RISC-V is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation.
This talk will summarize the benefits of RISC-V and open ISAs for the open-source systems-software community. The first section of the talk will focus on the draft RISC-V privileged specification, including the RISC-V vision for cleaner abstraction between hardware, hypervisors, and operating systems.
The talk will also discuss my experience bringing up RISC-V emulation support in QEMU, including adding architectural support, experimental devices, and fuzz testing against Spike, the “golden-reference” RISC-V simulator. The talk will conclude by outlining opportunities to contribute to RISC-V ISA support in QEMU.
Sagar Karandikar is a Ph.D. Candidate in computer architecture at UC Berkeley. His research focuses on HW/SW co-design for hyperscale systems. His work has been used in over 50 peer-reviewed publications from authors at over 20 institutions and in the development of commercially-available... Read More →
Thursday August 25, 2016 11:15am - 12:00pm EDT
Pier 3
With this presentation, Mihai Dontu will explain what virtual machine introspection is trying to achieve, talk about previous research and current status on other platforms. He will then list the areas of the KVM hypervisor that needed enhancing to accommodate such technologies, and some of the more notable roadblocks which were overcome.
I lead the Linux development team at Bitdefender and I am currently involved in integrating our HVI technology with open source hypervisors like Xen and KVM
Thursday October 26, 2017 11:15am - 12:00pm EDT
Palmovka
Turbo modes allow CPUs to operate above their specified base frequency. Modern CPUs change frequency dynamically and often due to CPU load, power consumption, temperature, cooling capacity of the system, and CPU SKU. A socket with half of its CPUs idle may run its active CPUs at a higher frequency than a socket with all CPUs busy.
VMs expect consistent performance, which is in tension with turbo in a datacenter. A lightly-loaded host may provide better VM performance than a heavily-loaded host, and hosts have varying levels of load that are not directly visible to the VMs. Datacenter forensics on performance variation is valuable, but turbo effects were invisible to our performance monitoring trackers.
This talk discusses upstream patches that track a VM’s per-VCPU turbo history. We describe turbo observations and measuring turbo occupancy per VM in our datacenters.
In para-virtual networking with virtio-net/vhost, the copying of packet between the hypervisor and the guest is one of the major sources of the overhead, especially for the large packets. And, although, zero-copy transmit was merged into the Linux kernel a few years ago, the "receive side zero copy" item is still in the KVM NetworkingTodo.
This talk presents an approach to implementation of zero-copy receive for virtio-net and vhost that leverages receive-side steering abilities of the modern high speed network cards.
Network Function Virtualization, a network architecture where virtual machines replace components such as firewalls or load balancers with virtual machines, can be very sensitive to network latency or throughput. A typical NFV architecture under KVM uses components such as Open vSwitch, DPDK and vhost-user; despite the pecularities (such as handling packets in user space during whole process, consuming multiple cores with 100% to polling the network ports), this can provide good network performance. However, configuration of the various components and of the virtual machine itself is very important to obtain the best possible network performance.
In this talk we will show how to configure Open vSwitch, DPDK and vhost-user, and present throughput and latency results that quantify the impact of hugepages and multiqueue and the importance of using the "PREEMPT_RT" realtime kernel.
VIRTIO as a para-virtualized device decouples VMs and physical devices. Friendly live-migration support makes it well recognized by the cloud networking. However, the north-south I/O throughput of VIRTIO doesn’t compare with SR-IOV. The technical talk gives a practical proposal to address this by introducing a framework for vhost data path offloading. It essentially allows using HW device to offload the vring data path on the vhost side, without requiring the HW device being pass-thru to the guest. As a result, it achieves SR-IOV like performance with compatible live-migration support which makes it possible to upgrade a stock VM using virtio to a new HW accelerated platform transparently. Steve is going to explain the mechanism under the hood, go through the detail proposal, introduce the benefits, and share the WIP patch work and figure out the minimum HW prerequisite for doing this.
This talk will cover the challenge of improving VNFs safety relying on Virtio and Vhost-user backend on host side. Maxime will first provide a brief overview of a VNF architecture relying on Virtio/Vhost-user, to take the opportunity to highlight the possible safety concerns. In a second time, he will talk about new developments that introduces IOMMU support to Vhost-user backend, as a follow-up of last year talk from Peter Xu and Wei Xu about introducing IOMMU support for Vhost-kernel backend, and will provide some benchmarks to show the impact of enabling this feature. Finally, Maxime will talk about the remaining safety and performance gaps, and present the envisaged ways to fill them.
Tranditional teloc equipments use lots of hardware accelerators, how to leverage these accelerators becomes important in Network Function Virtualization(NFV). We are trying to implement a software solution based on KVM, to offload specific processing like encryption/decryption, media transcoding etc, this prestation will introduce an para-virtualization scheme of hardware accelerator, including introducing virtio frontend driver and backend device, making use of Linux kernel cryptography framework in the relization of virtio crypto frontend driver. I will present the advantages and current status of virtio crypto device, show the performance figure which compared to plain-soft scheme etc.
Software Testing practitioners are aware of testing strategies that exceed the developer's usual approach to test. While it is understandable that the two roles are inherently different, there are some strategies (and tools) that can greatly benefit how code is tested during development.
This talk will present the theory behind techniques such as Equivalence Partitioning, Boundary Value Analysis and Combinatorial Testing backed by real world virtualization code and use cases.
Finally, to break out of the boring theoretical space, practical demonstrations of these techniques will be applied to QEMU subsystems. This will tie the concepts and examples into improved test cases and extended test coverage.
Qemu provides many powerful storage backends supporting several disk format types. In some cases, however, it may be a design requirement to have a single process managing a storage backend for multiple VMs (similar to what vhost-user-net delivers for networking).
To bring the same concept for storage, we are introducing vhost-user-scsi. This is a new Qemu backend now merged in master which allows a separate process to take ownership of a virtio-scsi device. The flexibility of this model allows such an application to be implemented as a single process for multiple controllers or as one process per controller for added isolation.
In this joint talk by Nutanix and Intel we will introduce the vhost-user-scsi backend, discuss its implementation in Qemu and show how it can be used to achieve amazing performance when integrated with SPDK to explore local and remote NVMe controllers.
QEMU's limited RDMA support leaves it behind other modern hypervisors. Marcel and Yuval will present an implementation of an emulated RDMA device, analyse its performance and usability, and finally talk about future plans for a possible virtio-rdma device.
QEMU command line interface is large and increasingly complex. The infrastructure supporting it no longer meets the growing demands: it is insufficiently expressive for some configuration needs, and its introspection features are inadequate.
In this presentation, we will briefly explore how the command line traditionally works, and where it falls short. I will then present ongoing work to make it match QMP in expressiveness and introspection features. Customary ritual sacrifice to backward compatibility will be performed throughout.
The QEMU translation engine, the TCG, supports tens of architectures. Such a large support is possible thanks to the decoupling of the interpretation of input instructions and the generation of the translated code through the usage of an intermediate representation: the tiny code instructions.
Lifting instructions to an IR is of great interested in several fields outside emulation. Specifically, binary analysis tools (such as IDA Pro, BAP, angr and binary.ninja) often struggle to support many architectures due to the difficulty in interpreting the exact behavior of each instruction of an ISA.
This talk presents challenges and opportunities in the ongoing effort (bit.ly/2t9j8PV) to expose the TCG frontend to external applications. We'll discuss the build system, the design of the API, how to expose helper functions (e.g., FP and syscall implentations) and a real use case, rev.ng.
QEMU is a powerful multi-platform emulation tool, but it lacks debugging and instrumenting capabilities. QEMU includes only GDB server and some execution logging. Guest code may be instrumented by inserting callbacks and helper instructions into the translated code. In this talk we'll cover the problems that occur when creating the QEMU-based instrumentation tools (instrumenting of the selected processes within VM, analysis with record/replay, intrusive and non-intrusive approaches), and review the existing approaches and insttumentation frameworks (PANDA, DECAF, PinOS, PEMU). We'll also present our efforts in creating instrumentation/introspection plugins for QEMU and adding new debugging stub - WinDbg server.
The roots of KVM are in Qemu, which was originally written as an emulator for running X86 Linux binaries on foreign architectures. Today linux-user emulation has become a sidenote in Qemu development, which tends to focus on Virtualization features. In this presentation Riku will review the current state of user-mode emulation and what use cases it still has. Riku will show how user-mode contributions can be tested and validated. Finally there will be a look forward, on how linux-user code can be improved, and discussion on it's place in greater Qemu/KVM ecosystem.
Vector processing has existed since the 60s and lives on in modern CPUs as SIMD instructions. They are the main driver of performance for computationally intensive workloads such as multimedia and simulation. Vector registers have grown from MMX's 64 bit to 512 bit wide vectors today. ARM's Scalable Vector Extensions (SVE) take this growth to its logical conclusion and make the size of the registers an implementation detail while allowing binaries to run on any SVE capable processor.
We need to consider the impact of vectors on the TCG. Currently time is spent marshalling vector data to normal registers before calling helper functions. We will discuss the path to supporting vectors as first-class TCG citizens and also cover the other challenges in correctly modelling behaviour and ask if we can move beyond helper functions and generate efficient JIT code in a generic way.
Alex started learning to program in the 80s in an era of classic home computers that allowed you to get down and dirty at the system level. After graduating with a degree in Chemistry he's worked on a variety of projects including Fruit Machines, Line Cards, CCTV recorders and point-to-multipoint... Read More →
Friday October 27, 2017 4:45pm - 5:15pm EDT
Palmovka
